Hong Kong PolyU Quantum Tunneling Transistor Breaks MOSFET Limit

On August 27, 2026, a research team led by Professor Hao Jianhua at the Hong Kong Polytechnic University (PolyU) published a landmark paper in Science (Vol. 393, Issue 6814) demonstrating a quantum tunneling field-effect transistor (TFET) that fundamentally challenges the switching voltage limits of conventional MOSFETs.

The transistor exploits quantum band-to-band tunneling as its primary carrier injection mechanism, rather than thermionic emission over a barrier—the mechanism that has governed transistor operation since the invention of the MOSFET. This distinction is critical: thermionic emission is subject to the Boltzmann limit, which imposes a fundamental floor on the subthreshold swing (SS) of 60 mV/decade at room temperature. Quantum tunneling bypasses this limit entirely.

The Bi/InSe Heterostructure Innovation

The key materials innovation is a bismuth (Bi) / indium selenide (InSe) heterostructure that creates an abrupt band alignment optimized for tunneling injection. The heterostructure combines:

• Bismuth: A semimetal with unique topological properties that serves as the source material, providing a high density of states at the tunneling interface.
• InSe: A 2D semiconductor with a direct bandgap of approximately 1.26 eV, serving as the channel material. InSe's atomically smooth surface and excellent carrier mobility make it ideal for forming clean van der Waals interfaces.

The van der Waals interface between Bi and InSe eliminates the dangling bonds and interface roughness that plague conventional semiconductor heterostructures, creating a tunneling junction with near-ideal characteristics.

Performance Metrics

The demonstrated device achieves several breakthrough metrics:

The switching voltage of approximately 160 mV represents a 5x reduction compared to state-of-the-art MOSFETs, which typically require 600-800 mV to transition from off to on states. This voltage reduction translates directly to power savings: dynamic power in CMOS scales with the square of supply voltage (P ∝ CV²f), so a 5x voltage reduction could yield up to 25x power reduction for equivalent performance.

Why This Matters for the Semiconductor Industry

The semiconductor industry has been approaching the limits of MOSFET scaling for over a decade. As transistors shrink below 5nm, the Boltzmann limit on subthreshold swing prevents further reduction of switching voltage, creating a power wall that constrains performance gains. Industry roadmaps have identified alternative device architectures—TFETs, negative capacitance FETs, and single-electron transistors—as potential solutions, but experimental demonstrations with competitive performance have been elusive.

The PolyU result is significant for several reasons:

1. Room temperature operation: Unlike many quantum device demonstrations that require cryogenic temperatures, this TFET operates at room temperature, making it relevant for practical applications.
2. Competitive on-current: The I₆₀ of ~10 μA/μm, while lower than MOSFETs, is sufficient for many low-power applications including IoT sensors, wearable electronics, and edge AI inference.
3. Reproducible fabrication: The van der Waals heterostructure approach is compatible with emerging 2D material fabrication processes, suggesting a path to manufacturability.

The Research Team and Context

Professor Hao Jianhua's group at PolyU's Department of Applied Physics has been working on 2D materials and quantum transport for over a decade. The Bi/InSe heterostructure builds on earlier work from the group on InSe field-effect transistors and bismuth-based topological devices.

The research was conducted in collaboration with several international institutions, combining PolyU's expertise in 2D materials synthesis and device fabrication with theoretical modeling from partner groups. The Science publication represents the culmination of approximately three years of focused effort on optimizing the tunneling junction.

Challenges Ahead

Despite the breakthrough, significant challenges remain before TFETs can replace MOSFETs in production:

• On-current gap: The ~10 μA/μm on-current is 10-50x lower than high-performance MOSFETs. For compute-intensive applications, this gap must be closed through architectural innovations or materials optimization.
• Manufacturing integration: 2D materials like InSe are not yet compatible with standard CMOS fabrication flows. Developing wafer-scale synthesis and integration processes remains a major engineering challenge.
• Reliability: The long-term reliability and variability of tunneling devices in production environments are not yet established.

Nevertheless, the PolyU demonstration provides the most compelling evidence to date that the Boltzmann limit is not an insurmountable barrier for transistor technology. As the industry searches for paths beyond conventional scaling, quantum tunneling FETs have moved from theoretical possibility to experimental reality—with a clear performance advantage in the metric that matters most for energy efficiency: switching voltage.