OpenAI, Broadcom Unveil AI-Designed Inference Chip Jalapeno

On June 24, 2026, OpenAI and Broadcom jointly unveiled Jalapeño, the first custom silicon designed from the ground up for large language model inference. The chip was fabricated on TSMC's 3 nm process, features a systolic-array architecture paired with Arm-based custom CPUs and Broadcom's Tomahawk switching silicon, and pairs a roughly 840 mm² compute die with HBM3E memory in an advanced CoWoS package. Its rated thermal design power is 700 W, though OpenAI's August testing showed sustained consumption at or below 550 W. OpenAI stated that the journey from initial design to manufacturing tape-out took approximately nine months, calling it the fastest ASIC development cycle on record for a high-performance semiconductor.

That speed did not come from a single breakthrough. OpenAI used its own frontier models — including GPT-Astra and Codex — to accelerate multiple stages of the design pipeline. According to Richard Ho, who leads OpenAI's hardware effort, the team deployed agents to multiply the effectiveness of every engineer, spawning hundreds of them to run verification, timing closure, and area optimizations overnight while sub-intelligences read logs, diagnosed problems, and adjusted tool parameters. At a Synopsys executive forum, Ho emphasized that this was far more complex than a straight-line code workflow; it was large-scale, domain-specific automation that compressed bottlenecks typically governed by human throughput. The company also reported that AI-generated kernels for selected attention and mixture-of-experts modules ran 1.5 to 1.8 times faster than hand-optimized versions, and that agent-assisted optimization reduced the SIMD unit area by 8 percent and the matrix engine area by 10 percent.

On August 25, 2026, OpenAI published its first measured performance results. Using benchmarks from the InferenceX suite, Jalapeño was compared against Nvidia's GB200 and GB300 across three model sizes: GPT-OSS 120B, DeepSeek R1 670B, and Kimi K2.5 1T. Peak per-watt throughput improved by roughly 1.9 times, 1.7 times, and 1.5 times respectively. End-to-end latency dropped by 1.7 times to 3.6 times. When held to a fixed time-between-tokens target, throughput gains ranged from 53.7 times to over 100 times — a figure that reflects the compounding effect of lower latency at equivalent quality. OpenAI also estimated that inference costs would be roughly 50 percent lower than on traditional AI GPUs, a claim tied to the chip's purpose-built architecture rather than raw transistor count.

Division of labor and the path to deployment

The Jalapeño project is a three-party industrial collaboration. OpenAI designed the chip architecture from scratch, drawing on deep knowledge of the kernels, memory movement patterns, networking, and serving behavior that frontier models demand. Broadcom handled physical silicon implementation, advanced packaging, and networking technology. Celestica took responsibility for board-level integration, rack systems, and scalable manufacturing. TSMC manufactured the 3 nm compute die. Greg Brockman, OpenAI's president and co-founder, framed the chip as part of a broader full-stack infrastructure strategy: by designing more of the stack in-house, OpenAI could serve more intelligence with greater efficiency and push advanced AI toward broader access.

The deployment roadmap is ambitious. OpenAI plans to begin gigawatt-scale data center installations with Jalapeño by the end of 2026, ramp production through 2027, and reach full volume in the first half of 2028. A second-generation chip is already in deep development, and a third generation is on the drawing board. The company's long-term compute target spans 10 gigawatts of installed acceleration capacity — a figure that places this chip at the center of OpenAI's vertical-integration ambitions rather than at the periphery.

What the nine-month claim does and does not mean

The nine-month figure refers specifically to the interval from initial design to manufacturing tape-out — the point at which the final design files are sent to the foundry for mask-making and fabrication. It does not include silicon validation, yield ramp-up, system integration, or software maturation, all of which still lie ahead. SemiAnalysis reported that the broader project, from design kickoff to the CoWoS packaging tape-out milestone in November 2025, spanned closer to sixteen months, suggesting that the nine-month window may reflect the most compressed segment of a longer effort. OpenAI's official language — from initial design to manufacturing tape-out in just nine months — does not specify whether the starting point includes early architectural exploration or only the formal RTL design phase.

Context matters. A conventional high-performance AI ASIC typically requires 18 to 36 months from concept to tape-out; Google's first TPU took roughly three years, and Nvidia's H100 GPU cycle was about 24 months. Even against the more conservative sixteen-month estimate, Jalapeño's development was notably faster than the industry norm. However, this speed benefited from Broadcom's decade of accumulated packaging expertise from its existing XPU programs, OpenAI's unique workload-level knowledge of frontier models, and a proprietary AI-agent toolchain — three conditions that are difficult to replicate simultaneously.

A measured view of the performance claims

All performance numbers published so far originate from OpenAI's own testing. The company has stated that a detailed technical report will follow in the coming months, but as of publication no independent third-party benchmark has confirmed the results. The comparison framework against GB300 also warrants scrutiny: per-watt throughput and latency are meaningful metrics for inference, but they depend heavily on workload, batch size, quantization scheme, and system-level configuration. A chip optimized for a narrow class of LLM inference workloads can outperform a general-purpose GPU on those specific tasks without invalidating the GPU's broader utility.

Still, the strategic signal is clear. When an AI lab uses its own models to help design a chip that runs those same models — and does so in under a year — it represents a feedback loop that no traditional semiconductor company can easily replicate. Whether that loop translates into durable hardware advantage depends on factors OpenAI cannot fully control: foundry capacity, packaging yield, and the pace at which competitors like Google, Amazon, and Nvidia close the same design-automation gap. For now, Jalapeño is less a finished product than proof that the timeline for building one has fundamentally changed.