PolyU Breaks Boltzmann Limit with Quantum Tunneling Transistor

A research team at The Hong Kong Polytechnic University (PolyU) has engineered a novel tunnelling field-effect transistor (TFET) using two-dimensional nanomaterials, breaking through the fundamental "Boltzmann tyranny" that has constrained transistor energy efficiency for decades. The findings, published in Science on 28 August 2026, mark a significant step toward ultra-low-power computing and next-generation AI chips.

The Boltzmann Bottleneck

Conventional complementary metal-oxide-semiconductor field-effect transistors (MOSFETs) — the building blocks of modern integrated circuits — rely on thermionic emission to drive charge carriers over an energy barrier. This mechanism imposes a hard physical floor: the subthreshold swing (SS), which measures how sharply a transistor switches between ON and OFF states, cannot drop below 60 mV per decade at room temperature. This "Boltzmann limit" has stalled voltage scaling and exacerbated static power dissipation as transistors shrink toward atomic dimensions.

The International Roadmap for Devices and Systems (IRDS) has identified TFETs as the most promising alternative to MOSFETs. By replacing thermionic emission with quantum tunnelling — where charge carriers pass through a barrier rather than surmounting it — TFETs can in principle achieve SS values below the 60 mV decade⁻¹ threshold. However, demonstrating a simultaneously high ON current and high switching ratio at sub-Boltzmann levels has remained a formidable challenge for over a decade.

The Bi/InSe Heterostructure Breakthrough

The PolyU team, led by Prof. Jianhua Hao — Head of the Department of Physics and Materials, Chair Professor of Materials Physics and Devices, and Associate Director of the PolyU-Wuhan Technology and Innovation Research Institute — fabricated an ultrathin heterostructure of alternating 2D bismuth (Bi) and indium selenide (InSe) layers using pulsed laser deposition (PLD).

The key innovation lies in exploiting the dimensional transformation of bismuth: in bulk form, bismuth is a semimetal, but when confined to 2D ultrathin layers with precise nanoscale control, it becomes a semiconductor. This creates an ideal energy band alignment that allows charge carriers to tunnel efficiently from the Bi layer into InSe through a quantum tunnelling mechanism. Dr. Zehan Wu, Research Assistant Professor in the Department of Physics and Materials at PolyU, served as first author of the Science paper.

The resulting Bi/InSe TFET achieved SS values well below the 60 mV decade⁻¹ thermionic limit across six orders of magnitude of current switching. The device exhibited an I₆₀ (the current level at the sub-Boltzmann transition point) of up to approximately 10 microamperes per micrometre and a current-switching ratio exceeding 10⁷. Operating at room temperature on silicon substrates, the transistor required a gate-voltage range of only 160 mV — a fivefold reduction from the 800 mV conventionally required.

Fabrication and Compatibility

A critical practical advance is the use of PLD to fabricate the 2D heterostructure. The research demonstrated that PLD can produce precise, wafer-scale 2D material layers — a capability essential for future ultra-short-channel transistors and for compatibility with existing integrated circuit manufacturing processes. Clean interfaces fabricated under vacuum, combined with band engineering informed by subthreshold swing physics, were instrumental in achieving the device's performance metrics.

Collaborative Research

The study was conducted in collaboration with researchers from the National University of Singapore, The Hong Kong University of Science and Technology, Peking University, and the Singapore University of Technology and Design. The multi-institutional effort brought together expertise in materials synthesis, device fabrication, and theoretical device physics.

Implications for AI and the Semiconductor Industry

The breakthrough arrives at a moment of acute strategic pressure. As AI workloads scale exponentially, the energy demands of data-centre computing have become a first-order concern for both cost and sustainability. Transistors that switch at sub-Boltzmann voltages directly reduce dynamic power consumption, which scales with the square of the supply voltage. A fivefold reduction in gate-voltage range — from 800 mV to 160 mV — implies a theoretical 25-fold reduction in dynamic power for equivalent switching performance.

Prof. Hao stated: "By adopting quantum tunnelling, our TFET breaks through this boundary, paving the way for ultra-low-power, high-performance integrated circuits essential for emerging AI chips and advanced semiconductor applications."

The IRDS roadmap positions TFETs as the leading candidate to succeed MOSFETs in next-generation logic. The PolyU result — meeting IRDS performance requirements with a silicon-compatible, room-temperature device — represents the closest a TFET has come to commercial viability. Whether PLD can be integrated into high-volume semiconductor manufacturing at competitive cost remains an open question, but the demonstration of wafer-scale 2D material fabrication removes a significant practical barrier.

Outlook

The Bi/InSe platform is not merely a single-device demonstration; it establishes a materials-design framework where dimensional confinement transforms semimetallic elements into semiconductors with engineerable band alignments. This approach could extend to other 2D heterostructure combinations, broadening the design space for post-MOSFET devices. For Hong Kong's semiconductor research ecosystem, the result reinforces the city's capacity to contribute foundational device-level innovations to the global chip supply chain — at a time when geopolitical pressures are reshaping where advanced semiconductor research is conducted and commercialised.