SEMIFIVE Begins Mass Production of HyperAccel's Bertha AI Chip

SEOUL — Korean fabless design house SEMIFIVE announced on September 8, 2026 that it has begun mass production of "Bertha," an LLM AI inference accelerator built for Korean startup HyperAccel, fabricated on Samsung Foundry's 4nm process. The chip is a "big die" design whose surface area exceeds 500 square millimeters, and SEMIFIVE said it delivered a complete turnkey solution spanning front-end design and verification through packaging, testing and volume manufacturing supply.

Bertha is HyperAccel's flagship data-center inference accelerator, built around its proprietary LPU (Language Processing Unit) architecture — a coarse-grained, transformer-optimized core that concentrates all its firepower on LLM inference rather than the general-purpose layout of a GPU. HyperAccel publishes these target specifications for Bertha 500 (figures are the vendor's own): 384 TFLOPS at FP16 and 768 TFLOPS at FP8 at a 1.5 GHz target clock, 128 GB (expandable to 256 GB) of LPDDR5X memory with 546 GB/s of bandwidth, 256 MB of on-chip SRAM, support for 1 to 1,024 concurrent requests per card, and a 250 W TDP in a dual-slot PCIe Gen5 form factor.

The most distinctive design choice is memory. Where Nvidia's data-center accelerators and most custom ASICs lean on HBM, Bertha uses low-cost LPDDR5X and attacks efficiency through data-movement optimization rather than raw bandwidth. HyperAccel CTO Lee Jin-won, a former Samsung System LSI engineer, told ChosunBiz that memory access — not raw compute — is the real inference bottleneck, arguing that GPUs achieve only about 50 percent memory-bandwidth utilization and that the LPU's buffer-minimized data path is designed to reach roughly 90 percent. The company claims this roughly doubles tokens-per-second versus an Nvidia H100 while materially lowering total cost of ownership; the CTO's stated goal is to cut server TCO to about one-third of a GPU-based setup by pairing cheaper DRAM with lower power.

SEMIFIVE's role and momentum

SEMIFIVE positions the program as proof of execution in advanced nodes. First-half 2026 bookings for new mass-production orders reached 42.3 billion won — nearly double the 21.2 billion won it booked across all of 2025 — with second-quarter order intake of 26.7 billion won up 71 percent sequentially. Bertha is the third such volume ramp in roughly a year, following the Wisenet 9 security-camera AI ASIC for Hanwha Vision in the third quarter of 2025 and an HPC AI chip for a Japanese customer in the second quarter of 2026. The company's CEO, who argued that the industry's shift from training to inference is driving surging demand for data-center ASICs, called the milestone a validation of its execution in advanced processes.

The company's Samsung axis is structural, not incidental: SEMIFIVE's president is a former Samsung Electronics System LSI executive, the company acquired Hanatec, a Samsung Foundry SAFE design-solution partner, and Samsung appears among its IP ecosystem partners. In other words, Bertha is the work of a domestic design house and a domestic foundry.

The production milestone also matches HyperAccel's stated roadmap. In a February 2026 interview with ChosunBiz, company CTO Lee Jin-won said the Bertha chip had completed design and was heading toward mass production in the second half of 2026 — the September announcement effectively delivers on that schedule. HyperAccel has been gathering customer and partner traction around the chip: a proof-of-concept with Naver Cloud that it plans to expand through Korea's K-Cloud project, work with LG Electronics on a lower-power on-device variant for appliances and robots, an MOU with Taiwanese industrial-device maker Advantech on AI infrastructure, and membership in the "independent foundation model" (독파모) consortium coordinated under Korea's sovereign-AI effort.

Analysis: a signal of the inference ASIC shift

The announcement is small in volume terms but concrete evidence of a broader re-alignment. (1) As inference — not training — becomes the dominant cost of running large models, the economics tilt toward specialization: an inference-only ASIC with a cheaper memory bill of materials and lower power can undercut a training-grade GPU built for generality. Bertha is an early, Korea-specific example of that logic. (2) The LPDDR-not-HBM strategy is the crux. It trades headline bandwidth for a radically lower bill of materials, betting that dataflow efficiency closes the gap. Whether that holds at scale is an open question — the roughly 90 percent utilization claim is the vendor's own and not yet independently verified. (3) Structurally, the program is a win for Samsung Foundry and Korea's domestic system-semiconductor ambitions — a homegrown core, a domestic ASIC integrator, and a domestic foundry stacked together — and it de-risks an unusually large 4nm inference die, a design-and-packaging challenge usually reserved for HPC. (4) It is not Nvidia displacement yet. Volume, yield quality, and a software ecosystem broader than vLLM and PyTorch will determine whether Bertha becomes a data-center mainstay or a niche product of Korea's K-Cloud / Naver-adjacent projects.